Project showcase
In this section I have compiled a selection of various projects that hopefully may interest a wider audience:
Right now, the list includes
Further projects with descriptions will added continuously.
Right now, the list includes
- TIA/TSC using Multifunction DAQ and LabVIEW
- Impedance analyzer front-end
- Test interface for super-capacitors
- Raspberry Pi timing monitor
- Off-air clock ensemble
- E-field antenna
- S/PDIF + AES/EBU analyzer
- Prototyping
- DCF77 reference design
- 32-bit D/A-converter
- 250 V DC power supply
- SCR crowbars and fuses
- Audio power amplifiers
- Filters
- Noise blanker
- PM 519x reference synthesizer
Further projects with descriptions will added continuously.
Multichannel Time-interval analyzer (TIA) and Time-stamping analyzer (TSC) with X-series DAQ and LabVIEW
In this project I use the National Instruments USB-6366 X-series synchronous sampling multifunction DAQ as the heart of an 8-channel time analyzer. The purpose is to provide monitoring of multiple frequency references. Control, data handling and reporting are all done in LabVIEW. The USB-6366 runs at just 2 MHz maximum sampling rate, but thanks to its 16-bit quantization it's possible to adopt interpolation to provide sub-nanosecond resolution of 1 pps signals. There will be two modes of the VI: Either it may run as a time-interval analyzer (measuring the difference between the reference channel and any of the other 7 input channels), or as a time-stamping analyzer (which assigns a time stamp to an edge on each of the 8 input channels). On the picture on the left you can see the spreading of 34 k time-interval readings for a rise-time limited signal being split up and connected to two inputs. The arithmetic mean is 1.67 ns with a standard deviation of 91.6 ps. In a similar project, a down-converter front-end allows comparison of 4 channels of 5 or 10 MHz clock signals using the USB-6366 X-series DAQ. The common clock from an OCXO is governed by a FLL implemented in LabVIEW, or as an alternative, an external DDS synthesizer may be used as the common clock. The system may be used as a monitor for multiple clock sources, and allows 3 or 4-cornered hat analyses. |
Impedance analyzer adaptor
Impedance analyzers and precision LCR measurement gear come with a substantial price tag. In this project a novel front end allows accurate impedance measurements by using commonly available sound cards or data acquisition modules. The prototype spans over mΩ to MΩ ranges without range switching, and from DC to above 100 kHz, using a Kelvin probe and with correction of the parasitic impedances and channel skew. The prototype includes configurable low-pass filters to accommodate DAQ-type modules without filtering of the A/D or D/A-converters. Further information is found on the impedance pages. |
Clock ensembling of LF services
In this project a receiver processes a multitude of services to provide one, stable output frequency with improved Allan variance and reduced probability of eg. cycle slips due to propagation issues. The receiver prototype system is partly modelled in LabVIEW and processes real-time data from the E-field antenna below, from my broadband loop antenna, or a number of ferrite loop antennas. The results so far are promising. The system calculates channel statistics, it derives updated weighting parameters and manages acquisition and holdover, when required. The design allows switching between FLL and PLL modes, and between different loop bandwidth settings, on the run. The first picture shows an example of real-time weighting of the MSF (60 kHz), RBU (66 2/3 kHz), DCF77 (77.5 kHz), France Inter (162 kHz), and the Droitwich (198 kHz) services. The graph below shows the resulting ADEV for the very first prototype (BLUE), using all of the 5 stations above as source. The OCXO used was a TrueTime 8666-C2S. Statistics in this example were made over 500 measurements of 720kS at 500 kHz sampling. Also shown are a traditional off-air reference (GREEN), the FS700 (VIOLET) and the LPRO-101 rubidium (RED). The ADEV of the prototype is comparable to that of the FS700, but long-term stability above 1ks could be improved further. |
Time monitoring with Raspberry Pi
The Raspberry Pi is a neat programming and controllling platform for timing applications. The target of this project is to develop a health monitor of multiple frequency sources between 1 and 20 MHz, with Ethernet access for off-site handling and statistics processing. The picture shows a preliminary test setup with the MTI Milliren model 260 OCXO (16.384 MHz) as the comparison master. |
E-field antenna for LF services
The antenna is intended for reception of multiple services, in particular MSF (60 kHz), RBU (66 2/3 kHz), DCF77 (77.5 kHz), Loran-C/eLoran (100 kHz), France Inter (162 kHz) and Droitwich (198 kHz). In order to decrease the physical height of the antenna it's constructed around a sphere rather than a rod or a long wire. The sphere has a diameter of about 28 cm, and a capacitance of 16 pF. A 10 mm rod with the same capacitance would be about 140 cm long. A wideband, low-distortion FET op-amp, the AD8065 from Analog Devices, is used as the input buffer, and the LM6171 from Texas Instruments is used as the output amplifier. A 4th order lowpass filter with 1 MHz cut-off located between the two amplifier stages limits the bandwidth. The antenna includes both BNC and XLR outputs. The antenna can be powered through its 2.1 mm DC inlet, or through the XLR connector. A gas discharge tube and transient voltage suppression (TVS) diodes take care of the input protection. |
NEW!
Picture on its way.
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Front-end for super-capacitor testing
This design allows flexible testing of high-value capacitors (a.k.a. "super-capacitors") for transport and other applications of energy storage. The front-end takes care of power management and monitoring, and is intended to be used together with existing DAQ-type modular instruments. The solutions permits the designer to adhere to different test schemes, including custom-made charge/discharge profiles. |
S/PDIF + AES/EBU analyzer
Poorly implemented digital audio sources and cabling imperfections challenge the clock recovery and D/A-conversion in digital audio equipment. This project targets physical layer analysis of digital audio interfaces such as S/PDIF and AES/EBU so that one may characterize the signal imperfections like jitter and pulse distortion. The design is based on wideband subsampling of the electrical S/PDIF or AES/EBU signals, and the final design will allow studio technicians and dedicated audiophiles to make sanity checks of digital audio installations using one convenient handheld device. |
Prototyping
A number of working prototypes have been made of add-on boxes, utilities and measurement gear in various form factors. The example of the left shows a frequency divider unit to provide a CMOS level sampling clock from a frequency reference. An input from 10 mV to 15 V RMS from 1 to 20 MHz is accepted to accommodate different sources. |
DCF77 reference design
Over an extended period of time I have carried out a series of experiments to characterize the long-wave time services and to investigate principles and design details for off-air frequency references. The objective is to establish a fresh framework and working knowledge for a new generation of off-air receivers. The experimental design on the left features a channel quality estimator, lock accelerator circuitry, and sliding loop bandwidth among other things, of which some is implemented as VHDL in a CPLD. The experience gained can be adopted to new designs, both analog and digital. |
32-bit resolution D/A-converter
For programmable voltage references and accurate OCXO control I have developed a digital to analog converter with up to 32-bit word input. The design is based on a Multi-Stage Noise Shaping (MASH) structure in combination with a 16-bit Pulse-Width Modulation (PWM) driver to ensure true 32-bit resolution and absolute monotonicity. The converter effectively behaves like a duty-cycle controlled divider of a reference voltage. The MASH and PWM stages were modelled in LabVIEW, and are implemented in VHDL in the final implementation. The key components include a programmable device (CPLD/FPGA), FET-switches with low charge injection, a low-drift voltage reference, a DC-accurate lowpass filter, and buffer circuitry. In other words, the design eliminates the need for expensive D/A-converter chips in applications where resolution is more important than speed. The upper picture shows the 16-bit result before the PWM output stage for a 32-bit unsigned decimal input word of 1234567890. The lower picture shows the spectrum of the above signal, over a total of 10k 16-bit words. The x-axis represents the time relative to the sample interval, and the y-axis is scaled in dB. The design is inherently free from spurs, as demonstrated by the spectrum analysis. |
NEW!
Picture on its way.
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Acquisition accelerator
The design helps speeding up the acquisition process in a PLL with a loop bandwidth so narrow that the pull-in effect will take much too long. The circuitry is based on previous experiments and consists basically of an auxiliary PLL and a frequency difference detector and can be added to most analog PLL designs. It's highly useful for eg. off-air receivers where the loop bandwidth has been reduced. |
NEW!
Picture on its way.
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Frequency Multiplier with Auto-adjusting Notch Filtering
A common tool in the time and frequency laboratory is a frequency multiplier to provide 10 MHz from 5 MHz references. Different designs have been published, but a recurrent challenge is to reduce the contents of the 5 MHz signal and the harmonics over the operational temperature range. The design presented here introduces a notch filter that adjusts itself automatically to ensure maximum suppression. |
Frequency reference for Fluke/Philips PM 519x and TTi TG1010 / Wavetek 29
The popular PM 5191 / PM5192 / PM5193 series of synthesizer function generators from Philips (later Fluke) is found in many laboratories around the globe. In its standard configuration the generator features an ordinary crystal oscillator. For precision applications, Philips/Fluke offered the S-version with 10 MHz reference input and a built-in reference synthesizer to generate the internal clock frequency. However, the reference synthesizer did not produce the correct clock frequency (2^33 mHz or 8.589934592 MHz), but 10 MHz * 9217/10730, which is 0.02 ppm off. In this project the goal was to synthesize the required internal reference frequency using an alternative DDS PLL. The final device accepts a 5 or 10 MHz signal from your local laboratory reference (GPS, rubidium, etc.), and provides the correct clock for the "EXT CLOCK" input of the PM 519x. With this, the PM519x may now be used as clock source for lock-in amplifiers, etc. The graph demonstrates how the phase noise of the frequency reference converter is small compared to the function generator. The upper line (green) shows the ADEV when comparing the TTL output of two PM5191 generators, both locked to the converter and set to 1 MHz, and measured with the HP 5370A. The ADEV when comparing the 2^33 mHz clock output of two converters is significantly better, represented by the line in blue, just above the noise floor of the 5370A, shown in purple. Encouraged by the results, I had to make a variant of the reference generator for the TTi TG1010 and Wavetek 29 families. These generators require 2^38 * 0.1 mHz or 27.4877906944 MHz as the reference frequency. Having no fan, the TTi TG1010 / Wavetek 29 generators are a pleasure to work with for longer periods of time. Thanks to the reference generator they can now also provide the needed frequency accuracy. The picture shows the Wavetek 29 with the reference generator above. There's a vast offering of DDS function generators on the market with larger phase accumulators and resolution in the μHz range, but the accuracy (being the proximity of the output frequency to the true value) when using their external reference input is not perfect. The internal sampling clock is often a neat round figure, like 40 MHz, 125 MHz and so on, derived from the 10 MHz reference input. As a result, the majority of frequency settings are truncated, seen as a systematic phase drift. With a 40 MHz sampling clock, you will be fine if you want a 5 or 10 MHz output, but a 77.5 kHz setting, for instance, will produce a phase drift too large for DCF77 applications. The solution with a dedicated DDS-PLL reference generator ensures that any frequency you may require will be spot on, without truncation errors, when using an external reference. |
Power supply projects
If you need a standard power supply they come in great numbers and are available at a reasonable price. However, for some applications you may want to build your own, perhaps for reasons of low noise, high programming speed, or the level of accuracy. The picture shows an example of a small DC supply I've used to power avalanche pulsers. It provides up to about 25 mA so you may even use it to power tube pre-amplifiers, if you're into tube electronics. The supply requires a transformer, rectifier diodes, and a capacitor for the high-voltage unregulated rail, and a regulated low voltage supply (about +15 V), which are not shown in the diagram. The design ensures that if the low voltage supply is removed the output will go low. Use and modify the design as you please, but beware of the potentially lethal voltages present. Apply all necessary safety measures to avoid personal injury. You may use other transistors than those shown here, as long as they can cope with the voltage with some margin. The output MOSFET will dissipate all the power when you short the output and has to be mounted on a heat sink. For higher output currents reduce the value of the current-sensing resistor, and arrange the required cooling of the output MOSFET. The picture shows my implementation of the design. I used a 200 V / 50 mA transformer, a BY179 bridge rectifier, and a 220 uF/320V capacitor for the high-voltage rail. The 15 V supply is located on a separate board located to the right close to the front panel. Most of the circuitry shown in the schematic diagram is found on the small board close to the heat sink. |
On SCR crowbars and fuses
For a project that involved lead accumulators as a power source there was a need for protection against overvoltage (not just transient voltages from electrostatic discharges) and wrong polarity. At the same time, a low voltage drop was required. A couple of semiconductor companies offer overvoltage and surge stopper devices, but in this particular case the solution was to use an SCR and a shunt diode in combination with a fuse. A few design rules determine the ratings of the SCR and the diode to ensure safe operation with a specific fuse. The key is to use devices that can handle the current integral of the fuse; As a rule-of-thumb use an SCR with an I²t rating at least 4 times higher than that of the fuse. The same applies to the reverse voltage shunt diode. Secondly, the dI/dt for the SCR should be limited to the critical value for the particular device, preferably with a safety factor of 2. The picture shows a test setup used to carry out experiments and to validate the design. |
Audio amplifier projects
The two pictures show representative work on audio power amplifiers: An experimental modification of an amplifier design from a commercial receiver to test non-switching bias circuitry (upper picture), and a bottom-up design of a 500 W PA mono stage (lower picture). After the modifications the amplifier not only produced better measurement results, it also sounded a lot better. As a bonus the amplifier now can be switched on and off without annoying thuds and bumps (!). The bias circuitry allows one channel to use bipolar transistors while the other channel uses MOSFETs, without any adjustments. The PA mono stage includes non-switching bias circuitry based on the findings from the preceeding experiments, soft-clipping, surge current limiter, and a thoroughly symmetrical design that allows switching on and off without a speaker relay. The work on this PA mono stage resulted in a framework for the design of power amplifiers. |
Filters
Various filters, both active and passive, have been carved out for different purposes, spanning from sub-Hz frequencies to the GHz range. One filter to emphasize is this 10 kHz low-pass filter with inherent low distortion to be used during testing of eg. power amplifiers. The filter attenuates the 3rd harmonic from a generator with more than 95 dB, and thanks to high-quality high-voltage film capacitors in combination with the abscense of ferruginous materials you can reach 3rd order harmonic distortion below -150 dB. The toroid coils reduce the mutual coupling and the coupling to objects in the surroundings. |
Noise blanker
In this project the objective was to investigate the principles for noise blanking and to develop a noise blanker to be used for the longwave band, both broadcast and time services. The blanker includes a pulse detecting circuitry, an RF switch and a delay line. The picture shows the circuit that was used to carry out the experiments. |